Apple
Apple
Posted 3 months ago
Full Time
Austin, Texas
In Person
Smart Summary
Responsibilities
The engineer will correlate RTL performance against model performance and identify bottlenecks to improve SoC design. They will also define performance statistics and methodologies to support multi-functional engineering efforts.
Qualifications
You have a Bachelor's degree and foundational experience in CPU & SOC architecture/design. You will perform deep performance analysis, identify bottlenecks, and correlate RTL performance against models, requiring strong interpersonal skills and the ability to work independently.
Must Have Skills for ATS
RTL
CPU architecture
SOC architecture
Verilog
C/C++
SystemVerilog
Perl
Python
Job Description
Apple
With Runway
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